arm - Process address space and PTE's User/Kernel bit -


most of modern processors implement paging (for memory management) , in paging ptes (page table entry) including user/kernel bit restrict unwanted access. why bottleneck? there reason why don't way:

process address space divided on user , kernel space, of course. , direct reason implement 2 ptprs (page table pointer register) can see on arm. simple logic on hw level can divide logical address user , kernel space. now, both modes have own page table entries except want share (i assume wouldn't share pages want access restricted kernel). so, there no reason implement user/kernel bit, isn't so? missing something?


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