fpga - Entries in Verilog always sensitivity list -

can't find on this, doesn't fit in keywords. somewhere came across statement it's bad practice put things in block sensitivity list. things other clk , other related internal signals within device can, according statement, cause routing inefficiencies.

i find convenient when coding relatively slow applications generate subdivided clock signals, , use these in blocks.

for example:

reg counter [12:0]    ; reg slowclk   ;  @ (posedge clk)     begin     counter <= counter + 13'h1   ;     slowclk <= counter[12]    ;     end  @ (posedge slowclk) 

note: text entry has 1 statement per line, if lines concatenated in final post, that's due website.

is there wrong this?

yes indeed bad practice. can different slowclk edge.

you can take wire, detect slowclk positive edge.

wire got_slowclk_posedge;  

now detect, slowclk, positive edge, need have it's current , next clock values (current clock value should 0 & next clock value should 1) fortunately, in case, slowclk, next clock value current value of counter[12]. can use it.

assign got_slowclk_posedge = counter[12] & ~slowclk; 

so 2nd block may :

// instead of @(posedge slowclk) @(posedge clk) begin   if(got_slowclk_posedge)   begin     // code positive edge of slowclk   end end