cortex m3 - ARM Thumb/Thumb-2 performance -

i working on arm cortex-m3 controller has thumb-2 instruction set.

thumb mode used compress instruction 16-bit size. size of code reduced. normal thumb mode, why said performance reduced?

in case of thumb-2, said performance improved per these 2 links:

• wikipedia
• arm.com

improve performance in cases single 16-bit instruction restricts functions available compiler.

a stated aim thumb-2 achieve code density similar thumb performance similar arm instruction set on 32-bit memory.

what performance? can give few examples related it?

when compared against arm 32 bit instruction set, thumb 16 bit instruction set (not talking thumb2 extensions yet) takes less space because instructions half size, there performance drop, in general, because takes more instructions same thing on arm. there less features instruction set, , instructions operate on registers r0-r7. apples apples comparison more instructions same thing slower.

now thumb2 extensions take formerly undefined thumb instructions , create 32 bit thumb instructions. understand there more 1 set of thumb2 extensions. armv6m adds couple dozen perhaps. armv7m adds 150 instructions thumb instruction set, dont know armv8 or future hold. assuming armv7m, have bridged gap between can in thumb , can in arm. thumb2 reduced arm instruction set thumb is, not reduced. might still take more instructions same thing in thumb2 (assume plus thumb) compared arm doing same thing.

this gives taste of issue, single instruction in arm , equivalent in thumb.

arm  , r8,r9,r10  thumb  push {r0,r1} mov r0,r8 mov r1,r9 , r0,r1 mov r1,r10 , r0,r1 mov r8,r0 pop {r0,r1} 

now compiler wouldnt that, compiler know targeting thumb , things differently choosing other registers. still have fewer registers , fewer features per instruction:

mov r0,r1 , r0,r2 

still takes 2 instructions/execution cycles , 2 registers together, without modifying operands, , put result in third register. thumb2 has 3 register , single instruction using thumb2 extensions. , thumb2 instruction allows r0-r15 on of 3 registers thumb limited r0-r7.

look @ armv5 architectural reference manual, under each thumb instruction shows equivalent arm instruction. go arm instruction , compare can arm instruction cant thumb instruction. 1 way path thumb instructions (not thumb2) have 1 one relationship arm instruction. thumb instructions have equivalent arm instruction. not arm instructions have equivalent thumb instruction. should able see exercise limitation on compilers when using thumb instruction set. armv7m architectural reference manual , @ instruction set, , compare "all thumb variants" encodings (the ones include armv4t) , ones limited armv6 and/or v7 , see expansion of features between thumb , thumb2 thumb2 instructions have no thumb counterpart. should clarify compilers have work between thumb , thumb2. can go far compare thumb+thumb2 full blown arm instructions (armv7 ar called?). , see thumb2 gets lot closer arm, lose example conditionals on every instruction, conditional execution in thumb becomes comparisons branching on code, in arm can have if-then-else without branching...