verilog - Simulation of Modelsim launching from Quartus doesn't work properly -


this test bench

`timescale 1 ps/ 1 ps  module sum_fix_vlg_tst();  reg select; reg [7:-8] valor_a; reg [7:-8] valor_b;   // wires                                                wire [8:-8]  result_fx;  sum_fix i1 (  .result_fx(result_fx), .select(select), .valor_a(valor_a), .valor_b(valor_b)  );  initial                                                 $monitor ("valor_a = %b, valor_b = %b, result_fx = %b", valor_a,  valor_b,result_fx);  initial begin                                                   #10 select = 1; valor_a = 32'b0000000011111111; valor_b = 32'b0000000011111111;  #20  valor_a = 32'b1111111111111111; valor_b = 32'b1111111111111111;  #30  valor_a = 32'b1001100111001000; valor_b = 32'b0001111000111101;  end                                                      endmodule

and uut

`timescale 1 ps/ 1 ps module sum_fix (valor_a,valor_b,result_fx,select);  input [7:-8] valor_a,valor_b; output reg [8:-8] result_fx; input select;   always@ (valor_a or valor_b) begin  if (select==1) result_fx = valor_a + valor_b; else     result_fx = valor_a - valor_b; end  endmodule

compiled in quartus well. launch modelsim this: tools > rtl simulation. launch modelsim gives me lot of zzzzzzzzzzzzz in input , xxxxxxxxxxxxxx in output without in wave.

i want i'm not sure if added testbench correctly project. i'm beginer. did was: assignments > settings > compile test: click test benches > new, looked file , add, , ok. i'm not sure correct way, because looks complex. please on this.

also, comment initiate test bench writter template in quartus, ended changing file, final result code above.

so, tried code on edaplayrgound (http://www.edaplayground.com/x/cyc), , looks fine me. (you give run yourself, if you'd like).

you're seeing x's because @ time 0, haven't specified values of inputs (since delay 10 timesteps before assigning anything). consider either removing first #10, or putting assignments before it.

(x = unknown value; z = high impedance, means neither 1 nor 0 input).

as setting in quartus, way did correct.


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