VHDL Counter ones errors -

i done code, , can work, however, when try write test bench, got troubles on that. input x sets 8 bits, , x: in bit_vector (n -1 downto 0). when write test bench connot enter bits number.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity count_ones    generic (n: integer := 8); -- number of bits    port ( x: in bit_vector (n -1 downto 0); y: out natural range 0 n); end entity ;  architecture behavioral of count_ones     type count array (n downto 1) of natural;     signal : count;  begin    a(0) <= 1 when (x(0) = '1')   else        0;   gen: in n-1 downto 0   generate             a(i+1) <= (a(i)+1) when (x(i)='0')             else                   a(i); end generate;  y <= a(n-1);  end behavioral; 

the test bench:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity count_ones_tb end count_ones_tb;  architecture behavior of count_ones_tb    component count_ones port(      x : in  std_logic_vector(7 downto 0);      y : out  std_logic_vector(0 3)     );  end component;  --inputs signal x : std_logic_vector(7 downto 0) := (others => '0');  --outputs signal y : std_logic_vector(0 3);   begin  -- instantiate unit under test (uut) uut: count_ones port map (       x => x,       y => y     );  stim_proc: process begin                 x <= "00010101";         wait 100 ns;             x <= "00001001";         wait 100 ns;         x <= "11111111101"         wait 100ns;   -- insert stimulus here     wait; end process;  end; 

the error

entity port x not match type std_logic_vector of component port entity port y not match type std_logic_vector of component port

please me, real cannot figure out way solve that.

the answer specific question types of ports in entity, ports in component , types of signals must match. here link code errors , many more corrected.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity count_ones    generic (n: integer := 8); -- number of bits    port ( x: in bit_vector (n -1 downto 0); y: out natural range 0 n); end entity ;  architecture behavioral of count_ones     type count array (n downto 0) of natural;     signal : count;  begin    a(0) <= 1 when (x(0) = '1')   else        0;   gen: in n-1 downto 0   generate             a(i+1) <= (a(i)+1) when (x(i)='0')             else                   a(i); end generate;  y <= a(n-1);  end behavioral;  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity count_ones_tb end count_ones_tb;  architecture behavior of count_ones_tb    component count_ones    generic (n: integer := 8); -- number of bits    port ( x: in bit_vector (n -1 downto 0);            y: out natural range 0 n);  end component;  --inputs signal x : bit_vector(7 downto 0) := (others => '0');  --outputs signal y : natural;   begin  -- instantiate unit under test (uut) uut: count_ones port map (       x => x,       y => y     );  stim_proc: process begin                 x <= "00010101";         wait 100 ns;             x <= "00001001";         wait 100 ns;         x <= "11111101";         wait 100ns;   -- insert stimulus here     wait; end process;  end; 

however must point out long way achieving goal of trying count number of ones.

because of that:

1. my corrections code not correct answer. in fact, corrections not answer. have made minimum corrections make code compile , run. need think type ports , signals in design should be.
2. my corrections not make code work, i.e. count number of ones.